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absolute maximum ratings supply voltage, v cc rf differential input voltage rf input dc offset port voltage charge pump dc offset varactor drive dc offset crystal dc offset buffered reference output data, clock and enable dc offset storage temperature junction temperature mp14 thermal resistance chip to ambient, ja chip to case, jc features complete 2.4 ghz single chip system (for faster device refer to sp5768) optimised for low phase noise, with comparison frequencies up to 4 mhz no rf prescaler selectable reference division ratio reference frequency output selectable charge pump current integrated loop amplifier two switching ports low power replacement for sp5658 and sp5668 power consumption 110mw with v cc = 5?v and all ports off downwards software compatible with sp5658 esd protection 2kv min., mil-std-883b method 3015 cat.1 (normal esd handling procedures should be observed) applications tv, vcr and cable tuning systems communications systems description the SP5748 is a single chip frequency synthesiser designed for tuning systems up to 2.4 ghz and is optimized for low phase noise with comparison frequencies up to 4 mhz. it is designed to be downwards software compatible with the sp5658. the rf programmable divider contains a front end dual-modulus 416/17 functioning over the full operating range 3-bit latch and port/test mode interface 4 16/17 4-bit count 13-bit count 17-bit latch 6-bit latch reference divider ref crystal cap crystal pump drive data interface data clock enable rf input port p0/op port p1/oc 9 2 3 1 14 8 7 11 12 5 6 4 charge pump SP5748 2.4ghz very low phase noise pll datasheet ds4875 issue 2.3 november 2001 ordering information SP5748/kg/mp1s (tubes) SP5748/kg/mp1t (tape and reel) (14 lead minature plastic package) SP5748/kg/qp1s (tubes) SP5748/kg/qp1t (tape and reel) (16 lead qsop plastic package) figure 1 SP5748 block diagram (mp14 pinout) and allows for coarse tuning in the up-converter application and fine tuning in the down-converter. comparison frequencies are obtained either from a crystal controlled on-chip oscillator or from an external source. a buffered reference frequency output is also available to drive a second SP5748. the device also contains 2 switching ports. -0?v to +7v 2?v -0? to v cc +0?v -0? to v cc +0?v -0? to v cc +0?v -0? to v cc +0?v -0? to v cc +0?v -0? to v cc +0?v -0? to v cc +0?v -55 c to +125 c +150 c 81 c/w 27 c/w
2 SP5748 datasheet figure 2 - pin connections - top view mp14 sp 5748 1 2 3 4 5 6 7 14 13 12 11 10 9 8 charge pump crystal cap crystal enable data clock port p1/oc drive v ee rf input rfinput v cc ref portp0/op qp16 charge pump crystal cap crystal enable data clock port p1/oc port p0/op drive v ee nc rf input rf input nc v cc ref 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 sp 5748 electrical characteristics test conditions (unless otherwise stated): tamb = -40 c to +80 c, v cc = 4?v to 5?v. these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. note: pin numbers refer to mp14 package. characteristic conditions max. min. value typ. units 150mhz to 2400mhz, see figure 6 80mhz to 150mhz, see figure 6 see figure 3 all input conditions v pin1 = 2v, see table 1 v pin1 = 2v, v cc = 15?v, t amb = 25 c v pin14 = 0?v see figure 5 for application sinewave coupled via 10nf blocking capacitor sinewave coupled via 10nf blocking capacitor ac coupled, see note 1 2-20mhz pin 20 -400 300 300 v cc 0? 10 500 10 20 20 0? supply current rf input frequency range input voltage input impedance data, clock and enable input high voltage input low voltage input current hysteresis clock rate bus timing data set up data hold enable set up enable hold clock to enable charge pump output current output leakage drive output current crystal frequency external reference input frequency drive level buffered reference output output amplitude output impedance 10 11,12 5,6,4 6 5,6,4 1 1 14 2,3 2 9 80 30 40 3 0 -10 300 600 300 600 300 0? 2 2 0? 13 0? 3 0?5 250 ma mhz mvrms mvrms v v a vp-p khz ns ns ns ns ns a na ma mhz mhz vp-p vp-p ? cont
3 SP5748 datasheet functional description the SP5748 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete pll frequency synthesised source. the device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with excellent phase noise performance, even with high comparison frequencies. the block diagram is shown in figure 1 and packages and pin allocations in figure 2. the SP5748 is controlled by a standard 3-wire bus comprising data, clock and enable inputs. the programming word contains 26 bits, two of which are used for port selection, 17 to set the programmable divider ratio, 4 bits to select the reference division ratio (bits rd and r0-r2, see table 2), two bits to set charge pump current, bits c0 and c1 (see table 1) and the remaining bit to access test modes (bit t0, see table 3)). the programming data format is shown in figure 4. the clock input is disabled by an enable low signal, data is therefore only loaded into the internal shift registers during an enable high and is clocked into the controlling buffers by an enable high to low transition. this load is also synchronised with the programmable divider so giving smooth fine tuning. the rf signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. the output of the preamplifier is fed to the 17-bit fully programmable counter, which is of mn+a architecture. the m counter is 13 bits and the a counter 4 bits. the output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. this frequency is derived either from the on-chip crystal controlled oscillator or from an external reference source. in both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into1 of 16 ratios as described in table 2. the output of the phase detector feeds the charge pump and loop amplifier section, which when used with an external high voltage transistor and loop fiiter integrates the current pulses into the varactor line voltage. the charge pump current setting is described in table 1. a buffered crystal reference frequency suitable for driving further synthesisers is available from pin 9. if not required this output can be disabled by connecting to v cc . the programmable divider output divided by 2, f pd /2 and comparison frequency, f comp , can be switched to ports p0 and p1 respectively by switching the device into test mode. the test modes are described in table 3. electrical characteristics (continued) characteristic at 10khz ssb with 2mhz comparison from 4mhz crystal see table 2 see note 2 v port = 0?v v port = v cc conditions max. min. value units mhz dbc/hz ma a typ. 4 131071 320 10 2 comparison frequency equivalent phase noise at phase detector rf division ratio reference division ratio output ports p0 and p1 sink current leakage current pin 7,8 notes 1. reference output disabled by connecting to v cc . 2. output ports high impedance on power-up, with data, clock and enable at logic ?? -148 240 2
4 SP5748 datasheet j2 j1 j0.5 j0.2 0 2 j0.2 2 j0.5 2 j1 2 j2 1 0.5 0.2 j5 2 j5 2 5 0?ghz 1ghz 2?ghz figure 3 - rf input impedance s11: z o = 50 ? normalised to 50 ? figure 4 - data format 2 25 2 24 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 2 0 clock enable data p1 p0 t0 c1 c0 r2 r1 r0 rd msb lsb frequency data ? ? ? ? ? 2 16 to 2 0 programmable divider ratio control bits r2, r1, r0 reference divider control bits (see table 2) rd reference divider mode select (see table 2) p1, p0 port control bits (see table 3) c1, c0 charge pump current bits (see table 1) t0 test mode enable bit 39pf 18pf SP5748 2 3 figure 5 - crystal oscillator application 0 0 1 1 c1 0 1 0 1 c0 230 1000 115 500 charge pump current ( a) table 1 - charge pump current
5 SP5748 datasheet table 2 - reference divider control p1 test mode description x 0 0 1 1 p0 x 0 1 0 1 t0 0 1 1 1 1 table 3 - test modes normal operation charge pump sink charge pump source charge pump disable port p1= f comp , p0 = f pd /2 figure 7 - example of double conversion from vhf/uhf frequencies to tv if sl 5748 1 2 3 4 5 6 7 14 13 12 11 10 9 8 reference enable data clock control micro 39p 18p optional application using on-chip crystal controlled oscillator 68p 13.3k 15n 1n 1n 1 5v p1 p0 22k 1 30v bcw31 16k 47k 2.2n tuner oscillator output 1 12v figure 8 - typical application of SP5748 SP5748 2 3 10 vco 10n 3 SP5748 1650-2400mhz 50-900mhz 1.6ghz 38.9mhz 18p 39p 80 1000 2400 frequency (mhz) vin (mvrms into 50 ? ) 300 30 10 150 40 operating window figure 6 - typical input sensitivity 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 rd 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 r2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 r1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 r0 2 4 8 16 32 64 128 256 3 5 10 20 40 80 160 320 division ratio
6 SP5748 datasheet applications a generic set of application notes an168 for designing with synthesisers such as the SP5748 has been written, covering aspects such as loop filter design and decoupling. this application note is published on the zarlink semiconductor web site http:/www.zarlink.com. a generic test/demonstration board has been produced which can be used for the SP5748; the circuit diagram is shown in figure 9, with component values in table 4. the board can be used for the following purposes: measuring rf sensitivity performance. indicating port function. synthesising the voltage controlled oscillator. testing of external reference. measurement of phase noise performance. reference source the SP5748 offers optimal lo phase noise performance when operated with a large step size. this is due to the fact that the lo phase comparator noise within the loop bandwidth is: +20log 10 ( lo frequency ) phase comparator frequency assuming the phase comparator noise floor is flat irrespective of sampling frequency, this means that the best performance will be achieved when the overall lo there are two ways of achieving a higher phase comparator sampling frequency: (1) reduce the division ratio between the reference source and the phase comparator (2) use a higher reference source frequency. approach (2) may be preferred for best performance since it is possible that the noise floor of the reference osciliator may degrade the phase comparator performance if the reference division ratio is very small. loop bandwidth the majority of applications for which the SP5748 is intended require a loop filter bandwidth of between 2khz and10khz. typically the vco phase noise will be specified at both 1khz and10khz offset. it is common practice to arrange the loop filter bandwidth such that the 1khz figure lies within the loop bandwidth. thus the phase noise depends on the synthesiser comparator noise floor, rather than the vco. the 10khz offset figure should depend on the vco providing the loop is designed correctly, and is not underdamped. table 4 - component values for figure 9 c20 c21 led 1 led 2 r1 r4 r6 r7 r8 r9 r10 r11 r12 r13 r14 s1 t1 vco x1 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 component 18pf 2?nf 68pf 1nf 1nf 10nf 100nf 4? f 100nf 10pf 1nf 100pf 100pf 4?nf 100pf 4? f 10nf 39pf 100pf value/type component 1nf 1nf hlmpk-150 hlmpk-150 4?k ? 4?k ? 13?k ? 22k ? 1k ? 0 ? 16 ? 16 ? 16 ? 68 ? sw dip-2 bcw31 pos_2000 4mhz value/type
7 SP5748 datasheet figure 9 - SP5748 evaluation board sp 5748 1 2 3 4 5 6 7 14 13 12 11 10 9 8 data enable clock c3 r7 c2 c5 c4 v cc r8 1 30v t1 r9 r10 c14 rf3 comp output rf2 ext ref r1 r4 1 8v led1 led2 c1 1 lk1 c17 r11 r12 r13 c20 1 8v rf input rf1 c19 c21 r14 vco rf out vt 1 2 j2 varactor c15 c13 c12 j5 3 4 5 6 1 2 3 4 5 1 8v c8 c9 1 30v c16 c7 1 5v v cc j1 power connector 12 p1 p0 port outputs j4 vco tuning range = 1370mhz to 2000mhz c18 c1 c6 lk2 is fitted for normal operation s1 x1 r6 lk2
8 SP5748 datasheet figure 10 - SP5748 evaluation board layout bottom view top view
9 SP5748 datasheet figure 11a rf inputs v cc rf inputs 500 500 figure 11b loop amplifier v cc 200 charge pump drive figure 11c enable, data and clock inputs v cc 25k figure 11d output ports port figure 11e reference oscillator crystal v cc crystal cap figure 11f reference output ref v cc 1 2ma figure 11 - input/output interface circuits
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